One important measure of semiconductor electronic device performance is leakage current. Excessive leakage currents can be indicative of serious defects in the device. Many methods are employed to measure such leakage currents. One particularly relevant complication is the role that device speed (Kp) plays in determining whether a leakage current is too high or not. Many methods of measuring these two values are known and employed in device screening. All have significant limitations and shortcomings. Some of these existing methodologies are described as follows.
An IC (integrated circuit) device has a nominal amount of leakage from the power supply to the ground caused by the cumulative leakage of all associated transistors (source to drain leakage, substrate leakage, gate leakage, etc.). Under normal conditions all IC's have some leakage. This is defined as a baseline leakage current. As is known to those having ordinary skill, typical measures of such leakage include so-called Static Idd (SIDD) or quiescent leakage (Iddq). These can be measured when the device transistors are put in a known off-state with the proper conditioning pattern and test vector stop locations.
However, when certain defects are present in a device these leakage currents can become substantially elevated. For example, when a physical silicon defect exists in a transistor or along a wire line, the leakage current may be substantially increased above its normal baseline level. Typically, this can be caused by either a direct path from the power supply to ground or from the inability to turn off all transistors as intended by the test pattern used to measure leakage current. By detecting the elevated leakage current, test routines can be used to identify devices that have certain defects and thereby screen out defective parts that may not be functional in the field or pose a reliability issues over the lifetime of the device.
In the prior art a number of methods have been tried to effectively measure this leakage current and screen devices using these measurements. In one approach, all devices having a leakage current in excess of a fixed leakage limit are deemed defective and discarded. In this approach the speed of the devices is not considered. In another approach, in order to test devices, each device is constructed with a specially constructed test cell formed in the device. The test cell is configured to measure device speed which is then related to an intrinsic leakage value associated with that device's speed. One such cell type is the PROCMON cell used by LSI Logic Corporation to measure device speed (Kp). This value is associated with measured values of leakage current. Using the leakage and device speed data obtained from each cell (each device) a picture of device performance can be formed and used to eliminate devices having excessive leakage currents. In yet another embodiment of the prior art, the acceptable level of intrinsic leakage is statistically determined from a defined sample (e.g. one wafer lot, or one wafer) and outliers are thus eliminated in post-processing (SPP) evaluation of the sample.
Each of the previously discussed methodologies suffers from its own unique set of limitations. For example, when a fixed leakage current limit is employed, leakage current is used to screen all devices without regard for device speed (Kp). In such cases ineffective screening can occur. With advanced CMOS technologies and deep-submicron gates the intrinsic and therefore acceptable leakage level depends strongly on the exact dimension of the gates (CD) and other factors. Consequently, a fixed Idd limit is no longer suitable for screening leakage-inducing defects. Typically, a leakage limit set too low screens out too many otherwise functional devices. Setting the limit too low results in a failure to screen out defective devices. Accordingly, this prior art method results in either excessive and unjustified fallout or ineffective screening of true defects.
When a dedicated performance-measuring cell is used, the test cell is used to directly measure the speed of the device (Kp). Such cell usage generates its own unique set of problems and shortcomings. First, the method cannot be employed to test devices that do not have the cell. This is particularly problematic when other manufacturers devices (which may not have a test cell or use a different test cell for which the user cannot test) are employed as they cannot easily be harmonized into existing test regimes. Additionally, the used of such test cells takes up valuable real estate on the surface of the device. This results in less function in the device or the exclusion of other desired functions. Additionally, because the test cell necessarily takes up only a small portion of a device surface it is not necessarily sensitive to variations in transistor speed occurring elsewhere on the device. If the speed-measurement test cell happens to reflect a faster area of the device it will result in an overestimation of the acceptable amount of intrinsic leakage and hence a reduced ability to screen defects that cause higher leakage. On the other hand if the test cell is in a slower area of the device it will result in an underestimation of the acceptable intrinsic leakage and therefore may cause over-rejection of otherwise acceptable devices. Thus, many defects can be missed using such test cells.
Additionally, the most common method used for such detection, Statistical Post Processing (SPP) has a variety of deficiencies that are difficult to remedy. SPP consists of the taking of many measurements of leakage current as well as directly measuring the operating speeds (Kp) of the devices. This accumulated data is subject to processing after collection by the automated test equipment (ATE). Typically, such involved statistical processing is done “off-line”. The resulting statistical information allows for leakage-inducing defect screening based on the off-line analysis of statistical outliers from a given sample populations, e.g. wafer lot, dies across a wafer, device lots, and the like. This method requires automated data collection and downloading from the ATE to a server and the software to filter out “outliers” after wafer sort with the ability to “ink-out” defective dies from the wafer sort database. In most cases SPP is not suitable for packaged devices where the trace to the wafer source location of the die can be lost. Additionally, such analysis takes time. For example, adequate testing of a single wafer can take as long as an hour. Thus, the software execution time forces a great deal of temporal overhead into the process. This removes the ability to conduct any sort of “real-time” testing. Additionally, to be valuable, thousands of pieces of data are required to generate accurate data that can be used from lot to lot. Thus, many lots of dies or devices must be tested before even the first evaluations can be made. Furthermore such screening can only take place on wafer-sort data where a device's speed and leakage can be associated to a wafer or lot and compared to its peer distribution and it cannot be easily conducted in real-time on an isolated assembled device during final test Thus, such testing is of limited value at the ATE evaluation stage because the data is not obtained until much after the wafers have been taken off of the ATE's and are further on in the process. In short, this process is too slow to be effective.
The inventors have recognized that there is a need for improving existing testing methods. What is needed is a methodology for enabling faster and more complete testing to be performed that measures both leakage current and a parameter associated with device speed to enable quick and accurate screening to identify devices with excessive leakage currents. Moreover, there is a need for such methodology to take into consideration normal and expected global shifts in intrinsic leakage levels and compensate for them.